Recently, there are increasing demands for further refinement of circuit patterns for increasing the degree of integration of a large scale integrated circuit device (hereinafter referred to as the LSI) realized by using semiconductor. As a result, it has become very significant to thin an interconnect pattern included in a circuit.
Now, the thinning of an interconnect pattern by a conventional optical exposure system will be described on the assumption that positive resist process is employed. In this case, a line pattern means a portion of a resist film not exposed to exposing light, namely, a resist portion (a resist pattern) remaining after development. Also, a space pattern means a portion of the resist film exposed to the exposing light, namely, an opening portion (a resist removal pattern) formed by removing the resist film through the development. In the case where negative resist process is employed instead of the positive resist process, the definitions of the line pattern and the space pattern are replaced with each other.
When a pattern is formed by using the optical exposure system, a photomask in which a light-shielding pattern of Cr (chromium) or the like is drawn in accordance with a desired pattern on a transparent substrate (a substrate having a transparent property) of quartz or the like is conventionally used. In such a photomask, a region where the Cr pattern exists is a light-shielding portion that does not transmit exposing light of a given wavelength at all (having transmittance of substantially 0%) and a region where no Cr pattern exists (an opening) is a transparent portion that has transmittance equivalent to that of the transparent substrate (having transmittance of substantially 100%) against the exposing light. At this point, all mask patterns are drawn on the transparent substrate, and in the pattern exposure, the transparent substrate is irradiated from a back side (i.e., a side where the mask patterns are not provided), and therefore, the mask patterns are irradiated with the exposing light having passed through the transparent substrate. Accordingly, when the transmittance of a mask pattern against exposing light is herein argued, the absolute transmittance of each portion of the mask pattern is not used but relative transmittance obtained on the basis of the transmittance of a transparent substrate against the exposing light (100%) is used.
In the case where the photomask as described above is used for the exposure of a wafer where a resist has been applied, an image of light having passed through the mask is projected onto the wafer. In this case, a light-shielding portion of the mask corresponds to an unexposed portion of the resist and an opening (transparent portion) of the mask corresponds to an exposed portion of the resist, so that a desired resist pattern can be formed on the wafer. Accordingly, such a photomask, namely, a photomask composed of a light-shielding portion and a transparent portion against exposing light of a given wavelength, is designated as a binary mask.
It is, however, difficult to accurately form a fine pattern smaller than the exposure wavelength (the wavelength of the exposing light) by using the binary mask because of the light diffraction phenomenon. This is for the following reason: Since the amplitude intensity of a diffraction image of light passing through the mask and projected onto a wafer is reduced, the proportion of zero-order light corresponding to non-diffracted light, namely, the proportion of a noise component in an optical image, is increased, and hence, a clear image cannot be obtained. As a result, a dimension error of a pattern provided on the mask is enhanced in the projected light image, which makes it difficult to form a pattern with desired dimensional accuracy. Such a phenomenon is designated as increase of MEF (mask error factor). In recent LSIs in which patterns are desired to be formed under highly accurate dimensional control, the reduction of the MEF is particularly a significant problem.
As another problem caused by the light diffraction phenomenon, there is a phenomenon that even when a mask pattern is formed in a rectangular shape, a resist pattern formed through exposure of the mask pattern has round corners. In particular, in the formation of a resist pattern in a thin line shape, the roundness of the corners of the resist pattern leads to a phenomenon that the line ends of the resist pattern are formed in a recess position. Such a phenomenon causes significant defect in integration of an LSI.
FIGS. 26A and 26B are diagrams for explaining harmful influence of the roundness of the resist pattern corners on the integration of an LSI. Specifically, FIG. 26A shows an exemplified layout pattern in which transistors are disposed. As shown in FIG. 26A, a gate layer pattern 12 corresponding to a gate electrode of a transistor is disposed on an active layer pattern 11 corresponding to an active region. Also, contact patterns 13 each corresponding to a contact connected to a source region or a drain region are disposed on both sides of the gate layer pattern 12 on the active layer pattern 11. At this point, in order to increase the degree of integration of an LSI by providing transistors at a high density, it is necessary to reduce a region sandwiched between gate layer patterns 12 corresponding to transistors adjacent to each other (hereinafter referred to as the “opposing region”) and to reduce an external length of the gate layer pattern 12 extending beyond the active layer pattern 11 in the opposing region. Therefore, as shown in FIG. 26A, an external length A of the gate layer pattern 12 in the opposing region is smaller than an external length B of the gate layer pattern 12 in a region opposite to the opposing region (hereinafter referred to as the “non-opposing region”).
FIG. 26B is a diagram in which resist patterns of respective layers formed through exposure of the patterns of the respective layers of the layout pattern of FIG. 26A are overlaid. Specifically, as shown in FIG. 26B, the shape of a resist pattern 21 corresponding to the active layer pattern 11, the shape of a resist pattern 22 corresponding to the gate layer pattern 12 and the shape of a resist pattern 23 corresponding to the contact pattern 13 are overlaid. Furthermore, as shown in FIG. 26B, in the resist pattern 22 corresponding to the gate layer pattern 12, line ends are rounded to be formed in recess positions as compared with the desired mask dimension (i.e., the dimension of the gate layer pattern 12). In this case, in the non-opposing region where the external length B of the gate layer pattern 12 is relatively large, a desired gate length LgO at the center of the active region is realized as a width along the gate length of the resist pattern 22 at the end of the active region. However, in the opposing region where the external length A of the gate layer pattern 12 is not sufficiently secured, a width Lgl along the gate length of the resist pattern 22 at the end of the active region is smaller than the gate length LgO. When there is a part where a sufficient gate length cannot be secured at the end of the active region in this manner, a source-drain leakage current is increased in this part, and hence, the resultant LSI cannot be normally operated.
In this manner, when the phenomenon of the roundness of resist pattern corners occurs, it is difficult to reduce the opposing region sandwiched between gate layer patterns in a circuit layout in which a plurality of transistors are adjacent to one another and to reduce an external length of a gate in the opposing region. Therefore, it is a significant problem for the integration of an LSI to prevent the phenomenon of the roundness of resist pattern corners.
As a countermeasure for preventing the roundness of resist pattern corners, a method in which a pattern for shielding light is provided around each corner of a mask pattern has been proposed (for example, Patent Document 1). FIGS. 27A and 27B are diagrams for explaining a method disclosed in Patent Document 1, and specifically, a method in which a transmittance adjustment film is used for preventing the roundness of resist pattern corners. FIG. 27A is a diagram of a desired pattern to be formed through exposure. As shown in FIG. 27A, the desired pattern is a plurality of rectangular patterns 30 adjacent to one another. Also, FIG. 27B is a diagram for showing the plane structure of a photomask used for forming the desired pattern of FIG. 27A. It is noted that a transparent substrate is perspectively shown in FIG. 27B. As shown in FIG. 27B, light-shielding portions 51 corresponding to the desired pattern are provided on the transparent substrate 50. Furthermore, a transmittance adjustment film 53 is provided in each area 52 where transparent portions 54 cross each other between the light-shielding portions 51 (i.e., transparent portion crossing area). The transmittance adjustment film 53 is used for adjusting the quantity of light passing through the transparent portion 54, and when the transmittance adjustment film 53 is provided at the transparent portion crossing area 52, the quantity of light passing through this area 52 can be reduced. Thus, it is possible to prevent excessive light from passing through the transparent portion crossing area 52, so that a corner of a resist pattern corresponding to the transparent portion crossing area 52 and its periphery can be prevented from being rounded.
Patent Document 1: Japanese Laid-Open Patent Publication No. 7-219207